As the most common bus standard in the computer industry, PCIe 3.0-4.0 has taken a full 7 years, but PCIe 4.0 has not yet been fully popularized. PCIe 5.0 has already been completed, and PCIe 6.0 is also eager to try. The PCI-SIG organization officially announced at the developer conference a few days ago that the official version of the PCIe 6.0 standard will be released in 2021.
The initial draft of PCIe 6.0 v5.0 was completed in February of this year. Recently, it was reported that the final draft of v0.7 will be announced soon. However, the latest official information writes that it will be later this year, and the follow-up will have to go through v0. The final draft of .9 will be the 1.0 official version.
Among the three core chip manufacturers, processors and graphics cards have fully supported PCIe 4.0 and are the fastest;
NVIDIA's latest Ampere architecture A100 chip supports PCIe 4.0, and it is expected that the new generation of RTX gaming graphics cards will not be absent;
Although Intel has repeatedly emphasized that PCIe 4.0 is useless for games, next year’s 11th-generation desktop Core Rocket Lake-S will eventually add support. The existing Z490 motherboard is already prepared in hardware, and the server is expected to be released soon. 10nm Ice Lake-SP will take the lead.
In terms of PCIe 5.0, Intel’s first Agilex FPGA shipped in August last year supports it. According to the leaked roadmap, Intel’s next-generation server platform Sapphire Rapids will support it. It is also expected to bring DDR5 memory. AMD may have to wait until Zen 4 Architecture.
PCIe 6.0 continues to double the I/O bandwidth to 64GT/s in accordance with the tradition. In practice, PCIe 6.0 x1 has a unidirectional bandwidth of 8GB/s, PCIe 6.0 x16 with a unidirectional bandwidth of 128GB/s and a bidirectional bandwidth of 256GB/s.
PCIe 6.0 will continue the 128b/130b encoding method introduced in the PCIe 3.0 era, but will add a new pulse amplitude modulation PAM4 instead of PCIe 5.0 NRZ, which can pack more data in a single channel and at the same time, and low-latency forward error correction ( FEC) and related mechanisms to improve bandwidth efficiency.
Many people may wonder that the bandwidth of PCIe 3.0 is often not used up. What is the use of PCIe 6.0? Obviously it is not prepared for the consumer market, or even general enterprise-level and data center-level applications, but for fields that require ultra-high bandwidth such as cloud, artificial intelligence, machine learning, edge computing, etc., a single PCIe 6.0 x16 can support 800G Ethernet, as well as various accelerators, FPGAs, ASICs, storage, etc., please look forward to it!
