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The Width Of The Transmitted Data Channel
- Jun 22, 2018 -

Parallel interface refers to the interface standard that uses parallel transmission to transmit data. From the simplest parallel data register or dedicated interface IC chip such as 8255, 6820, etc., to more complex SCSI or IDE parallel interfaces, there are dozens of types. The interface features of a parallel interface can be described in two ways: 1. The width of the data channel transmitted in parallel, also known as the number of bits transmitted by the interface; 2. Additional interface control lines or interactions used to coordinate the parallel data transmission The characteristics of the signal. The width of the data can be from 1 to 128 bits or more, and the most commonly used is 8 bits, and 8 data bits can be transmitted at a time through the interface. The most commonly used parallel interface in the computer field is the so-called LPT interface.

During data entry: The input device sends the data to the interface while making "Data Entry Ready" valid. When the interface sends data to the input buffer register, the "data input reply" signal is asserted, and when the peripheral device receives the acknowledgement signal, the "data input ready" and data signals are deactivated. At the same time, the corresponding bit ("Data Ready") in the status register is valid for the CPU to query. Of course, interrupts can also be used to issue interrupt requests to the CPU. After the CPU reads the data, the interface automatically resets the "Data input ready" bit in the status register. Then, the CPU goes to the next input process.

In the data output process: When the data output by the CPU is sent to the data output buffer register, the interface will automatically clear the “ready to output” status bit in the status register, and send the data to the output device, after the output device receives the data, A reply signal is sent to the interface to tell the interface that the data has been received. After the interface receives the signal, it sets the “ready to output” status bit in the status register to “1”. Then, the CPU goes to the next output process.